The present invention, in some embodiments thereof, relates to programming for electronic memories and, more particularly, but not exclusively, to such programming when applied to resistance based memories, including those with multi-level cells.
Some Multi-Level-Cell memories suffer from nonlinearity in their switching mechanism, and this may be the case with resistive random access, or ReRAM, memory cells. Using fixed programming pulses leads to a non-uniform level distribution and state-dependent programming which burdens the controller and demands a modified programming technique.
In order to deal with such a problem, there are programming methods that propose to apply pre-known programming pulses according to the desired state or perform an iterative program and verify operations. The disadvantage of such programming methods is that they increase both energy and programming latency.
The main limitation of the existing programming solutions is that the controller has to know the desired pulse level value for programming in order to apply the appropriate pulses. Nevertheless, the programming operations lead to high programming latency and energy usage in some cases, and increase complexity due to the higher number of voltage regulators needed to supply different voltage levels. Furthermore, current programming methods must take into account device variations due to imperfections in the fabrication process, and how to control uniform level distribution in order to increase noise margin and process variation tolerance. Applying pre-selected programming pulses may lead to a limited cell capacity caused by the wide level distributions, as a result of not properly taking into account the variations caused by process variations.
Now considered in greater detail, Resistive Random Access Memory (ReRAM) are memory technologies, where data is stored within a resistive switch (memristor) as the resistance of the device. Storing data as resistance rather than electric charge provides for longer retention time since no energy is stored within the cell and therefore the cell cannot leak. Numerous materials have showed memristive behaviour, meaning they have a resistance which can be varied. Suitable ReRAM materials include many oxides and other dielectric materials, and such materials can be used to design ReRAM in a back-end-of-the-line (BEOL) CMOS process, as a cross point between metals. ReRAM therefore has the potential to be extremely dense, and low powered, with high endurance. The change in the memristor resistance is continuous and thus the memory cell can be programmed to different values, which allows the design of multi-level memory cells, cells that store more than a single bit, to increase density.
Reference is now made to FIGS. 1(a)-(b), which is a graph showing resistance behaviour of a memristor under input pulses of different length. Considering the non-linear nature of the memristor dynamic behaviour, resistance levels of the device cannot be uniformly distributed by applying a fixed programming voltage pulse as illustrated in FIG. 1(b). Rather, for a transition between different resistance levels to be successful, several programming steps are required. Different ReRAM programming techniques have been reported in the literature such as staircase programming and program and verify programming (P&V). These programming methods require several programming steps with different voltage pulses for each step. Hence, these techniques suffer from increased latency, energy, and complexity. Furthermore, potential memristor state tuning methods may increase area overhead dramatically, and increase energy usage as well if adopted in ReRAM.
As mentioned, the impact of process variations on resistance level distribution in multi-level control is large. Programming a cell in ReRAM may be achieved by applying a Constant Voltage Stress (CVS) across the cell, for a sufficient amount of time. In Single-Level Cell (SLC), two programming operations may be performed, RESET and SET, which program the cell respectively, from a low resistive state (LRS) to a high resistive state (HRS) and from HRS to LRS. Both RESET and SET are performed using a CVS of Vrst and Vset for a sufficient amount of time, namely, Trst and Tset.
Studies of the effect of RESET and SET operations on the resistance of the cell show that the switching is non-linear in a log-shaped manner as depicted in FIG. 1(a). In Multiple Level Cell (MLC) ReRAM, the levels are represented by different resistances of the cell in addition to the two boundary resistances, namely LRS and HRS. Hence, programming operation in MLC relies on using finer voltage pulses while considering the partitioning of a cell into a certain number of levels. Due to the log-shaped non-linear transition of the memristive device, applying identical voltage pulses changes the resistance in a non-uniform manner across the resistance range as shown in FIG. 1(b), which leads to an increase in erroneous read of cells.
The following discusses the effect of non-linearity on process variation tolerance of the MLC ReRAM, and previously proposed programming methods and their effect on programming latency and energy are discussed.
Controlling Uniformity of Level Distribution
Imperfections in the fabrication process of memristors may cause different cells within the memory array to behave slightly differently from each other. Denote a cell that can store N values within a N-level cell, and k bits per cell (2k=N). Due to process variation, each resistance level within the N-levels is represented by a resistance range, rather than a deterministic resistance value, as depicted in FIG. 2(a). The resistance range boundaries of level i are characterized by the slowest and fastest cells in the ReRAM that their resistance is denoted by, respectively, RiS and RiF.
IMPP—Incremental Magnitude Pulse Programming, and ILPP—Incremental Length Pulse Programming are demonstrated in FIGS. 3(a) and 3(b). Both ILPP and IMPP require a read operation prior to programming to adjust the applied pulse to the current and desired states of the memristor. Hence, both techniques are state-pulse dependent techniques. The extra read operation increases programming latency, complicates the voltage generators, and requires the involvement of a controller. Furthermore, pulse-state dependency restricts in-memory multi-valued computing as further discussed hereinbelow.
Another programming method to control uniform level distribution is Program and Verify (P&V). The P&V method relies on applying narrow voltage pulses with consecutively increasing magnitude, combined with read pulses between each programming pulse to verify whether the cell has reached the desired state, as illustrated in FIG. 3(c). In ReRAM, programming operations are usually initiated on a word line, and the controller is responsible for connecting or disconnecting the cells when the desired state is achieved, hence, P&V allows selective programming of cells while controlling tighter resistance level distributions and thus possibly allowing a higher capacity. However, P&V requires more programming iterations as compared to ILPP and IMPP, as well as enhanced participation from the controller, which increases the latency of the programming operation.
Additionally, it has been reported that P&V based on a narrow voltage ramp increases device-to-device variations compared to CVS programming. Hence, it is desired to develop a programming technique with fewer programming iterations and voltage generators (ideally a single applied voltage) for less energy and lower latency. To achieve uniform level distribution by applying identical pulses that correspond to the desired level, the memristor may behave linearly under CVS, as depicted in FIG. 2(c). For example, for N-level cell with linear transition under CVS of length T, a level i can be programmed using i identical pulses of length T/(N−1).